1. Technical Field
The present disclosure relates to a surge current compensating circuit; in particular, to a surge current compensating circuit capable of reducing a surge current generated from the supply power, and a comparator module having this surge current compensating circuit.
2. Description of Related Art
Most electronic apparatuses need a direct current (DC) supply power for providing the required power. When an output signal of the specific circuit (for example, the comparator circuit) transits (for example, changes to the high voltage level from the low voltage level), the specific circuit soon draws a large current (i.e. surge current) from the supply power, thus resulting in the unstable output current of the supply power. Therefore, the lifetimes and voltage stabilities of the specific circuit or the supply power are decreased.
Referring to FIG. 1, FIG. 1 is a circuit diagram of a typical comparator circuit. The comparator circuit 1 comprises multiple P-type transistors (for example, PMOS transistors) P1 through P3 and multiple N-type transistors (for example, NMOS transistors) N1 through N4. The sources of the P-type transistors P1 through P3 are electrically coupled to the supply power VDDA, the sources of the N-type transistors N3 and N4 are electrically coupled to the grounding voltage GND, and the gates of the N-type transistors N3 and N4 receive the bias signal VBIAS. The gate of the P-type transistor P1 is electrically coupled to the gate of the P-type transistor P2, the drain of the P-type transistor P1, and the drain of the N-type transistor N1, the drain of the P-type transistor P2 is electrically coupled to the gate of the P-type transistor P3 and the drain of the N-type transistor N2, and the gates of the N-type transistors N1 and N2 respectively receive the first input signal VIN and the second input signal VIP. The sources of the N-type transistors N1 and N2 are electrically coupled to the drain of the N-type transistor N3, the drain of the N-type transistor N4 is electrically coupled to the drain of the P-type transistor P3 and the output stage of the comparator circuit 1 to generate the output signal VOUT. By the above coupling manner, the N-type transistors N1 through N3 and the P-type transistors P1, P2 form a differential input stage, and the N-type transistor N4 and the P-type transistor P3 form an output stage.
Referring to FIG. 1 and FIG. 2, FIG. 2 is a waveform diagram showing the first input signal, the second input signal, and the current of the output stage in the typical comparator circuit. Before the time T1, when the first input signal VIN is far larger than the second input signal VIP, the current flowing through the N-type transistor N1 and the P-type transistor P1 is far larger than the current flowing through the N-type transistor N2 and the P-type transistor P2 (p.s. the summation current of the current flowing through the N-type transistor N1 and the P-type transistor P1 and the current flowing through the N-type transistor N2 and the P-type transistor P2 is denoted as the current I1), thus turning off the P-type transistor P3. Meanwhile, the N-type transistor N4 is turned on, thus the output signal VOUT is at the low voltage level, and the current I2 of the output stage associated with the comparator circuit 1 is almost zero.
Near the time T1, when the first input signal VIN gradually approaches to the second input signal VIP, and then becomes less than the second input VIP, the current flowing through the N-type transistor N1 and the P-type transistor P1 gradually decreases, and becomes less than the current flowing through the N-type transistor N2 and the P-type transistor P2, thus turning on the P-type transistor P3. Meanwhile, the output signal VOUT changes from the low voltage level to the high voltage level, and thus the current I2 of the output stage associated with the comparator circuit 1 gradually increases. Last, after the time T1, the first input signal VIN is far less than the second input signal VIP, the output signal VOUT maintains the high voltage level stably, and the current I2 of the output stage associated with the comparator circuit 1 is stable.
From the above descriptions, it can be known that the current I2 of the output stage associated with the comparator circuit 1 generated before the output signal VOUT transits is not the same as that generated after the output signal VOUT transits. Under the condition the most electronic apparatuses operate in the high frequency, the output signal VOUT of the output stage associated with the comparator circuit 1 transits frequently, and the current output from the supply power VDDA is unstable, thus decreasing the lifetimes and voltage stabilities of the comparator circuit 1 and the supply power VDDA.
In addition to the above typical comparator circuit, the typical comparator circuit with the auto-zero function is also provided currently. Referring to FIG. 3, FIG. 3 is a circuit diagram of a typical comparator circuit with the auto-zero function. Compared to the comparator circuit 1 in FIG. 1, the comparator circuit 3 further has multiple P-type transistors PA1, PA2, multiple isolation capacitors C1 through C3, and an N-type transistor NA1. The gates of the P-type transistors PA1 and PA2 receive an inverted auto-zero control signal AZB of an auto-zero control signal AZ, the drains of the P-type transistors PA1 and PA2 are respectively electrically coupled to the drains of the N-type transistors N1 and N2, and the sources of the P-type transistors PA1 and PA2 are respectively electrically coupled to the gates of the N-type transistors N1 and N2. The gate of the N-type transistor NA1 receives the auto-zero control signal AZ, the drain of the N-type transistor NA1 is electrically coupled to the drain of the N-type transistor N4, and the source of the N-type transistor NA1 is electrically coupled to the gate of the N-type transistor N4. Additionally, the gates of the N-type transistors N1 and N2 respectively receive the first input signal VIN through the isolation capacitor C1 and the second input signal VIP through the isolation capacitor C2, and the gate of the N-type transistor N4 is electrically coupled to the grounding voltage GND through the isolation capacitor C3 rather than being electrically coupled to the bias signal VBIAS. By the above coupling manner, when the auto-zero control signal AZ is asserted, the output signal VOUT is reset to a predetermined voltage level (return to a zero level, for example), but the current I2 of the output stage associated with the comparator circuit 3 is a non-zero stable current. When the auto-zero control signal AZ is deasserted, the comparator circuit 3 is equivalent to the comparator circuit 1 of FIG. 1.
Referring to FIG. 3 and FIG. 4, FIG. 4 is a waveform diagram showing the first input signal, the second input signal, the current of the output stage, and the auto-zero control signal in the typical comparator circuit with the auto-zero function. The auto-zero control signal AZ is asserted (i.e. logically high) merely during the period from time t0 through t1. Meanwhile, the P-type transistors PA1, PA2, P3, and the N-type transistors NA1, N4 are turned on, the output signal is reset to the predetermined voltage level regardless the first input signal VIN and the second input signal VIP, and the current I2 of the output stage associated with comparator circuit 3 is the non-zero stable current. When the auto-zero control signal AZ is deasserted (i.e. logically low), the comparator circuit 3 is equivalent to the comparator circuit 1 of FIG. 1, thus the current I2 of the output stage associated with the comparator circuit 3 generated before the output signal VOUT transits is not the same as that generated after the output signal VOUT transits, the current output from the supply power VDDA is unstable, and the lifetimes and voltage stabilities of the comparator circuit 3 and the supply power VDDA are decreased.